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Preliminary Technical Data
FEATURES
Six Degrees of Freedom Inertial Sensor ADIS16364
FUNCTIONAL BLOCK DIAGRAM
AUX_ ADC TEMPERATURE SENSOR MEMS ANGULAR RATE SENSOR SIGNAL CONDITIONING AND CONVERSION CALIBRATION AND DIGITAL PROCESSING AUX_ DAC
Tri-axis, 14-bit digital gyroscope with digital range scaling 75/sec, 150/sec, 300/sec settings Tri-axis, 14-bit digital accelerometer 5 g measurement range 330 Hz bandwidth 180 ms start-up time Factory-calibrated sensitivity, bias, and axial alignment Digitally controlled bias calibration Digitally controlled sample rate, up to 819.2 SPS External clock input enables sample rates up to 1200 SPS Digitally controlled filtering Programmable condition monitoring Auxiliary digital input/output Digitally activated self-test Programmable power management Embedded temperature sensor SPI-compatible serial interface Auxiliary, 12-bit ADC input and DAC output Single-supply operation: 4.75 V to 5.25 V 2000 g shock survivability Operating temperature range: -40C to +105C
CS SCLK OUTPUT REGISTERS AND SPI INTERFACE DIN DOUT
TRI-AXIS MEMS ACCELERATION SENSOR
ALARMS DIGITAL CONTROL POWER MANAGEMENT VCC
SELF-TEST
RST DIO1 DIO2 DIO3 DIO4
Figure 1.
APPLICATIONS
Medical instrumentation Robotics Platform control Navigation
GENERAL DESCRIPTION
The ADIS16364 iSensor(R) is a complete inertial system that includes a tri-axis gyroscope and tri-axis accelerometer. Each sensor in the ADIS16364 combines industry-leading iMEMS(R) technology with signal conditioning that optimizes dynamic performance. The factory calibration characterizes each sensor for sensitivity, bias, alignment, and linear acceleration (gyro bias). As a result, each sensor has its own dynamic compensation for correction formulas that provide accurate sensor measurements over a temperature range of -40C to +85C. The ADIS16364 provides a simple, cost-effective method for integrating accurate, multi-axis, inertial sensing into industrial systems, especially when compared with the complexity and investment associated with discrete designs. All necessary motion testing and calibration are part of the production process at the factory, greatly reducing system integration time. Tight orthogonal alignment simplifies inertial frame alignment in navigation systems. An improved SPI interface and register structure provide faster data collection and configuration control. By using a compatible pinout and the same package as the ADIS1635x family, systems that currently use the ADIS1635x family can upgrade their performance with minor firmware changes to accommodate scale factor adjustments. This compact module is approximately 23 mm x 23 mm x 23 mm and provides a flexible connector interface, which enables multiple mounting orientation options.
Rev. PrA
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07842-001
ADIS16364 ADIS16300
GND
ADIS16364 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Specifications..................................................................................... 3 Timing Specifications .................................................................. 5 Timing Diagrams.......................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Basic Operation................................................................................. 9
Preliminary Technical Data
Reading Sensor Data.....................................................................9 Device Configuration ...................................................................9 Burst Mode Data Collection ........................................................9 Output Data Registers ............................................................... 11 Calibration................................................................................... 11 Operational Control................................................................... 12 Input/Output Functions ............................................................ 13 Diagnostics.................................................................................. 14 Outline Dimensions ....................................................................... 16 Ordering Guide .......................................................................... 16
Rev. PrA | Page 2 of 16
Preliminary Technical Data SPECIFICATIONS
TA = -40C to +85C, VCC = 5.0 V, angular rate = 0/sec, dynamic range = 300/sec, 1 g, unless otherwise noted. Table 1.
Parameter GYROSCOPES Dynamic Range Initial Sensitivity Test Conditions Min 300 0.0495 Typ 375 0.05 0.025 0.0125 40 0.05 0.5 0.1 3 0.007 1.9 0.1 0.05 0.25 0.9 0.038 330 14.5 1400 Max
ADIS16364
Unit /sec /sec/LSB /sec/LSB /sec/LSB ppm/C Degrees Degrees % of FS /sec /sec /hr /sec/C /sec/g /sec/V /sec rms /sec/Hz rms Hz kHz LSB g mg/LSB % ppm/C Degrees Degrees % of FS mg mg m/sec/hr mg/C mg/V mg rms mg/Hz rms Hz kHz LSB C/LSB Bits LSB LSB LSB LSB V pF
TA = 25C, dynamic range = 300/sec TA = 25C, dynamic range = 150/sec TA = 25C, dynamic range = 75/sec Reference to z-axis accelerometer, TA = 25C Axis-to-frame (package), TA = 25C Best fit straight line TA = 25C, 1 TA = 25C, 1 , SMPL_PRD = 0x01 TA = 25C, 1 , SMPL_PRD = 0x01 Any axis, 1 (MSC_CTRL, Bit 7 = 1) VCC = 4.75 V to 5.25 V TA = 25C, 300/sec range, no filtering TA = 25C, f = 25 Hz, 300/sec, no filtering
0.0505
Sensitivity Temperature Coefficient Misalignment Nonlinearity Initial Bias Error In-Run Bias Stability Angular Random Walk Bias Temperature Coefficient Linear Acceleration Effect on Bias Bias Voltage Sensitivity Output Noise Rate Noise Density 3 dB Bandwidth Sensor Resonant Frequency Self-Test Change in Output Response ACCELEROMETERS Dynamic Range Initial Sensitivity Initial Sensitivity Tolerance Sensitivity Temperature Coefficient Misalignment Nonlinearity Initial Bias Error In-Run Bias Stability Velocity Random Walk Bias Temperature Coefficient Bias Voltage Sensitivity Output Noise Noise Density 3 dB Bandwidth Sensor Resonant Frequency Self-Test Change in Output Response TEMPERATURE SENSOR Scale Factor ADC INPUT Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Input Range Input Capacitance
300/sec range setting Each axis 25C
696 5
2449
Axis-to-axis, TA = 25C, = 90 ideal Axis-to-frame (package), TA = 25C Best fit straight line TA = 25C, 1 TA = 25C, 1 TA = 25C, 1
TA = 25C, no filtering TA = 25C, no filtering
1 1 50 0.25 0.5 0.3 15 0.2 0.35 0.3 2.5 9 0.4 330 5.5 60 0.14 12 2 1 4 2 0 +3.3 20 180
X-axis and y-axis TA = 25C output = 0x0000
During acquisition
Rev. PrA | Page 3 of 16
ADIS16364
Parameter DAC OUTPUT Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Output Range Output Impedance Output Settling Time LOGIC INPUTS1 Input High Voltage, VINH Input Low Voltage, VINL CS Wake-Up Pulse Width Logic 1 Input Current, IINH Logic 0 Input Current, IINL All Pins Except RST RST Pin Input Capacitance, CIN DIGITAL OUTPUTS1 Output High Voltage, VOH Output Low Voltage, VOL FLASH MEMORY Data Retention3 FUNCTIONAL TIMES4 Power-On Start-up Time Reset Recovery Time Sleep Mode Recovery Time Flash Memory Test Time Automatic Self-Test Time CONVERSION RATE Clock Accuracy Sync Input Clock POWER SUPPLY Power Supply Current Test Conditions 5 k/100 pF to GND For Code 101 to Code 4095 Min
Preliminary Technical Data
Typ 12 4 1 5 0.5 0 2 10 2.0 CS signal to wake up from sleep mode 20 VIH = 3.3 V VIL = 0 V 0.2 -40 -1 10 ISOURCE = 1.6 mA ISINK = 1.6 mA Endurance2 TJ = 85C Time until data is available Normal mode, SMPL_PRD 0x09 Low power mode, SMPL_PRD 0x0A Normal mode, SMPL_PRD 0x09 Low power mode, SMPL_PRD 0x0A Normal mode, SMPL_PRD 0x09 Low power mode, SMPL_PRD 0x0A Normal mode, SMPL_PRD 0x09 Low power mode, SMPL_PRD 0x0A SMPL_PRD = 0x01 SMPL_PRD = 0x01 to 0xFF 2.4 0.4 10,000 20 180 250 60 130 4 9 17 90 12 0.413 819.2 3 1.2 5.25 10 -60 0.8 0.55 +3.3 Max Unit Bits LSB LSB mV % V s V V V s A A mA pF V V Cycles Years ms ms ms ms ms ms ms ms SPS % kHz V mA mA A
Operating voltage range, VCC Low power mode at 25C Normal mode at 25C Sleep mode at 25C
4.75
5.0 24 49 500
1 2
The digital I/O signals are driven by an internal 3.3 V supply, and the inputs are 5 V tolerant. Endurance is qualified as per JEDEC Standard 22, Method A117, and measured at -40C, +25C, +85C, and +125C. 3 The retention lifetime equivalent is at a junction temperature (TJ) of 85C as per JEDEC Standard 22, Method A117. Retention lifetime decreases with junction temperature. 4 These times do not include thermal settling and internal filter response times (330 Hz bandwidth), which may impact overall accuracy.
Rev. PrA | Page 4 of 16
Preliminary Technical Data
TIMING SPECIFICATIONS
TA = 25C, VCC = 5 V, unless otherwise noted. Table 2.
Normal Mode (SMPL_PRD < 0x09) Min1 Typ Max 0.01 2.0 9 40 48.8 100 24.4 48.8 5 12.5 5 12.5 5 5 600 833 Low Power Mode (SMPL_PRD > 0x0A) Min1 Typ Max 0.01 0.3 75 100 48.8 100 24.4 48.8 5 12.5 5 12.5 5
ADIS16364
Parameter fSCLK tSTALL tREADRATE tCS tDAV tDSU tDHD tSCLKR, tSCLKF tDF, tDR tSFS t1 t2 t3
1
Description Stall period between data Read rate Chip select to clock edge DOUT valid after SCLK edge DIN setup time before SCLK rising edge DIN hold time after SCLK rising edge SCLK rise/fall times DOUT rise/fall times CS high after SCLK edge Input sync pulse width Input sync to data ready output Input sync period
Burst Mode Min1 Typ Max 0.01 1.0 1/fSCLK 48.8 100 24.4 48.8 5 5 5 12.5 12.5
Unit MHz s s ns ns ns ns ns ns ns s s s
Guaranteed by design and characterization, but not tested in production.
TIMING DIAGRAMS
CS
tCS
1 SCLK 2 3 4 5 6 15 16
tSFS
tDAV
DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB
tDSU
DIN W/R A6 A5
tDHD
A4 A3 A2 D2 D1 LSB
07482-002
Figure 2. SPI Timing and Sequence
tREADRATE tSTALL
CS
Figure 3. Stall Time and Data Rate
t3 t2 t1
SYNC CLOCK (DIO4) DATA READY
07482-004
Figure 4. Input Clock Timing Diagram
Rev. PrA | Page 5 of 16
07482-003
SCLK
ADIS16364 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Acceleration Any Axis, Unpowered Any Axis, Powered VCC to GND Digital Input Voltage to GND Digital Output Voltage to GND Analog Input to GND Operating Temperature Range Storage Temperature Range
1
Preliminary Technical Data
Rating 2000 g 2000 g -0.3 V to +6.0 V -0.3 V to +5.3 V -0.3 V to VCC + 0.3 V -0.3 V to +3.6 V -40C to +105C -65C to +125C1, 2
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4. Package Characteristics
Package Type 24-Lead Module JA 39.8C/W JC 14.2C/W Device Weight 16 grams
Extended exposure to temperatures outside the specified temperature range of -40C to +85C can adversely affect the accuracy of the factory calibration. For best accuracy, store the parts within the specified operating range of -40C to +85C. 2 Although the device is capable of withstanding short-term exposure to 150C, long-term exposure threatens internal mechanical integrity.
ESD CAUTION
Rev. PrA | Page 6 of 16
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADIS16365
AUX_ADC
ADIS16364
TOP VIEW (Not to Scale)
SCLK DIO3 DIO1 DIO2 GND GND DNC DNC VCC DIN
1
3
5
7
9
11
13
15
17
19
21
23
2
DIO4/CLKIN
4
DOUT
6
CS
8
RST
10
VCC
12
VCC
14
GND
16
DNC
18
DNC
20
AUX_DAC
22
DNC
24
DNC
Figure 5. Pin Configuration
Figure 6. Axial Orientation
Table 5. Pin Function Descriptions
Pin No. 1 2 16, 17, 18, 19, 22, 23, 24 3 4 5 6 7 8 9 10, 11, 12 13, 14, 15 20 21
1
Mnemonic DIO3 DIO4/CLKIN DNC SCLK DOUT DIN CS DIO1 RST DIO2 VCC GND AUX_DAC AUX_ADC
Type1 I/O I/O N/A I O I I I/O I I/O S S O I
Description Configurable Digital Input/Output. Configurable Digital Input/Output or Sync Clock Input. Do Not Connect. SPI Serial Clock. SPI Data Output. Clocks output on SCLK falling edge. SPI Data Input. Clocks input on SCLK rising edge. SPI Chip Select. Configurable Digital Input/Output. Reset. Configurable Digital Input/Output. Power Supply. Power Ground. Auxiliary, 12-Bit DAC Output. Auxiliary, 12-Bit ADC Input.
S is supply, O is output, I is input, N/A is not applicable.
Rev. PrA | Page 7 of 16
07570-005
NOTES 1. CONNECTOR PINS ARE NOT VISIBLE FROM THE TOP VIEW. 2. THIS REPRESENTATION DISPLAYS THE TOP VIEW PINOUT FOR THE MATING SOCKET CONNECTOR. 3. DNC = DO NOT CONNECT.
DNC
ADIS16364 TYPICAL PERFORMANCE CHARACTERISTICS
1
Preliminary Technical Data
ROOT ALLAN VARIANCE (/sec)
0.1
0.01
0.001 0.1 1 10 100 INTEGRATION TIME (sec) 1k
10k
07482-007
Figure 7. Gyroscope Allan Variance
Figure 8. Accelerometer Allan Variance
Rev. PrA | Page 8 of 16
Preliminary Technical Data BASIC OPERATION
The ADIS16364 is an autonomous sensor system that starts up after it has a valid power supply voltage and begins producing inertial measurement data at a sample rate of 819.2 SPS. After each sample cycle, the sensor data loads into the output registers and DIO1 pulses, providing a new data ready control signal for driving system-level interrupt service routines. In a typical system, a master processor accesses the output data registers through the SPI interface, using the hook-up shown in Figure 9. Table 6 provides a generic, functional description for each pin on the master processor. Table 7 describes the typical master processor settings normally found in a configuration register and used for communicating with the ADIS16364.
I/O LINES ARE COMPATIBLE WITH 3.3V OR 5V LOGIC LEVELS 5V VDD
10 11 12
ADIS16364
Table 8 provides the lower byte address for each register, and Figure 10 provides the generic bit assignments.
07482-110
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UPPER BYTE
LOWER BYTE
Figure 10. Output Register Bit Assignments
READING SENSOR DATA
Although the ADIS16364 produces data independently, it operates as a SPI slave device, which communicates with system (master) processors using the 16-bit segments displayed in Figure 11. Individual register reads require two 16-bit sequences. The first 16-bit sequence provides the read command bit (R/W = 0) and the target register address (A6 ... A0). The second sequence transmits the register contents (D15 ... D0) on the DOUT line. For example, if DIN = 0x0A00, then the content of XACCL_OUT shifts out on the DOUT line during the next 16-bit sequence. The SPI operates in full duplex mode, which means that the master processor can read the output data from DOUT while using the same SCLK pulses to transmit the next target address on DIN.
SYSTEM PROCESSOR SPI MASTER
SS SCLK MOSI MISO IRQ
6
CS SCLK DIN DOUT DIO1
13
ADIS16300
SPI SLAVE
3
5
DEVICE CONFIGURATION
The user register memory map (see Table 8) identifies configuration registers with either a W or R/W. Configuration commands also use the bit sequence displayed in Figure 12. If the MSB is equal to 1, the last eight bits (DC7 ... DC0) in the DIN sequence load into the memory address associated with the address bits (A5 ... A0). For example, if the DIN = 0xA11F, then 0x1F loads into Address Location 0x26 (ALM_MAG1, upper byte) at the conclusion of the data frame. Most of the registers have a backup location in nonvolatile flash memory. The master processor must manage the backup function. Set GLOB_CMD[3] = 1 (DIN = 0xBE01) to execute a manual flash update (backup) operation, which copies the user registers into their respective flash memory locations. This operation takes 50 ms and requires the power supply voltage to be within the specified limit to complete properly. The FLASH_CNT register provides a running count of these events for managing the long-term reliability of the flash memory.
4
7
14
15
07482-009
Figure 9. Electrical Hook-Up Diagram
Table 6. Generic Master Processor Pin Names and Functions
Pin Name SS IRQ MOSI MISO SCLK Function Slave select Interrupt request Master output, slave input Master input, slave output Serial clock
Table 7. Generic Master Processor SPI Settings
Processor Setting Master SCLK Rate 2 MHz1 CPOL = 1 CPHA = 1 MSB-First 16-Bit
1
Description The ADIS16364 operates as a slave. Normal mode, SMPL_PRD[7:0] 0x08. Clock polarity. Clock phase. Bit sequence. Shift register/data length.
BURST MODE DATA COLLECTION
Burst mode data collection offers a more process-efficient method for collecting data from the ADIS16364. In 10 sequential data cycles (each separated by one SCLK period), all nine output registers clock out on DOUT. This sequence starts when the DIN sequence is 0011 1110 0000 0000 (0x3E00). Next, the contents of each output register are output from DOUT, starting with SUPPLY_OUT and ending with AUX_ADC (see Figure 12). The addressing sequence shown in Table 8 determines the order of the outputs in burst mode.
For burst mode, SCLK rate 1 MHz. For low power mode, SCLK rate 300 kHz.
The user registers provide addressing for all input/output operations on the SPI interface. Each 16-bit register has two 7-bit addresses: one for its upper byte and one for its lower byte.
Rev. PrA | Page 9 of 16
ADIS16364
Table 8. User Register Memory Map
Name FLASH_CNT SUPPLY_OUT XGYRO_OUT YGYRO_OUT ZGYRO_OUT XACCL_OUT YACCL_OUT ZACCL_OUT XTEMP_OUT YTEMP_OUT ZTEMP_OUT AUX_ADC N/A XXGYRO_OFF YXGYRO_OFF ZXGYRO_OFF XACCL_OFF YACCL_OFF ZACCL_OFF ALM_MAG1 ALM_MAG2 ALM_SMPL1 ALM_SMPL2 ALM_CTRL AUX_DAC GPIO_CTRL MSC_CTRL SMPL_PRD SENS_AVG SLP_CNT DIAG_STAT GLOB_CMD
1
Preliminary Technical Data
Flash Backup Yes No No No No No No No No No No No N/A Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes Yes No No N/A Address1 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x10 0x12 0x14 0x16 0x18 0x1A 0x1C 0x1E 0x20 0x22 0x24 0x26 0x28 0x2A 0x2C 0x2E 0x30 0x32 0x34 0x36 0x38 0x3A 0x3C 0x3E Default N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0006 0x0001 0x0402 0x0000 0x0000 0x0000 Function Flash memory write count Power supply measurement X-axis gyroscope output Y-axis gyroscope output Z-axis gyroscope output X-axis accelerometer output Y-axis accelerometer output Z-axis accelerometer output X-axis gyroscope temperature measurement Y-axis gyroscope temperature measurement Z-axis gyroscope temperature measurement Auxiliary ADC output Reserved X-axis gyroscope bias offset factor Y-axis gyroscope bias offset factor Z-axis gyroscope bias offset factor X-axis acceleration bias offset factor Y-axis acceleration bias offset factor Z-axis acceleration bias offset factor Alarm 1 amplitude threshold Alarm 2 amplitude threshold Alarm 1 sample size Alarm 2 sample size Alarm control Auxiliary DAC data Auxiliary digital input/output control Miscellaneous control Internal sample period (rate) control Dynamic range/digital filter control Sleep mode control System status System command Bit Assignments N/A Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 Table 9 N/A Table 10 Table 10 Table 10 Table 11 Table 11 Table 11 Table 22 Table 22 Table 23 Table 23 Table 24 Table 18 Table 16 Table 17 Table 13 Table 15 Table 14 Table 21 Table 12
R/W R R R R R R R R R R R R N/A R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R W
Each register contains two bytes. The address of the lower byte is displayed. The address of the upper byte is equal to the address of the lower byte, plus 1.
CS SCLK DIN DOUT R/W D15 A6 D14 A5 D13 A4 D12 A3 D11 A2 D10 A1 D9 A0 D8 DC7 D7 DC6 D6 DC5 D5 DC4 D4 DC3 D3 DC2 D2 DC1 D1 DC0 D0 R/W D15 A6 D14 A5 D13
07482-111
NOTES 1. DOUT BITS ARE BASED ON THE PREVIOUS 16-BIT SEQUENCE (R = 0).
Figure 11. Output Register Bit Assignments
CS 1 2 3 4 5 9 10
SCLK
DIN
0x3E00
DON'T CARE
07482-012
DOUT
PREVIOUS
SUPPLY_OUT
GYRO_OUT
XACCL_OUT
YACCL_OUT
YINCL_OUT
AUX_ADC
Figure 12. Burst Mode Read Sequence
Rev. PrA | Page 10 of 16
Preliminary Technical Data
OUTPUT DATA REGISTERS
Figure 6 provides the positive measurement direction for each inertial sensor (gyroscope and accelerometers). Table 9 provides the configuration and scale factor for each output data register in the ADIS16364. All inertial sensor outputs are 14 bits in length and are in twos complement format, which means that 0x0000 is equal to 0 LSB, 0x0001 is equal to +1 LSB, and 0x3FFF is equal to -1 LSB. The following is an example of how to calculate the sensor measurement from the XGYRO_OUT:
XGYRO_OUT = 0x3B4A 0x000 - 0x33B4A = -0x04B6 = -(4 x 256 + 11 x 16 + 6) - 0x04B6 = -1206 LSB Rate = 0.05/sec x (- 1206 ) = -60.3/sec
C1 VCC D R1 C2
07842-011
ADIS16364
D
Figure 14. Equivalent Analog Input Circuit (Conversion Phase: Switch Open, Track Phase: Switch Closed)
CALIBRATION
Manual Bias Calibration
The bias offset registers in Table 10 and Table 11 provide a manual adjustment function for the output of each sensor. For example, if XGYRO_OFF equals 0x1FF6, the XGYRO_OUT offset shifts by -10 LSBs, or -0.125/sec. The DIN command for the upper byte is DIN = 0x9B1F; for the lower byte, DIN = 0x9AF6. Table 10. XGYRO_OFF, YGYRO_OFF, ZGYRO_OFF
Bits [15:13] [12:0] Description Not used. Data bits. Twos complement, 0.0125/sec per LSB. Typical adjustment range = 50/sec.
Therefore, an XGYRO_OUT output of 0x3B4A corresponds to a clockwise rotation about the z-axis (see Figure 6) of 60.3/sec when looking at the top of the package. Table 9. Output Data Register Formats
Register SUPPLY_OUT XGYRO_OUT1 YGYRO_OUT1 ZGYRO_OUT1 XACCL_OUT YACCL_OUT ZACCL_OUT XTEMP_OUT2 YTEMP_OUT2 ZTEMP_OUT2 AUX_ADC
1 2
Bits 12 14 14 14 14 14 14 12 12 12 12
Format Binary, 5 V = 0x0814 Twos complement Twos complement Twos complement Twos complement Twos complement Twos complement Twos complement Twos complement Twos complement Binary, 1 V = 0x04D9
Scale 2.42 mV 0.05/sec 0.05/sec 0.05/sec 1 mg 1 mg 1 mg 0.14C 0.14C 0.14C 0.81 mV
Table 11. XACCL_OFF, YACCL_OFF, ZACCL_OFF
Bits [15:12] [11:0] Description Not used. Data bits, twos complement 1 mg/LSB. Typical adjustment range = 2 g.
Gyroscope Automatic Bias Null Calibration
Set GLOB_CMD[0] = 1 (DIN = 0xBE01) to execute this function, which measures XGYRO_OUT and then loads XGYRO_OFF with the opposite value to provide a quick bias calibration. Then, all sensor data resets to 0, and the flash memory updates automatically (50 ms). See Table 12.
Assumes that the scaling is set to 300/sec. This factor scales with the range. Note that typically, +25C, these registers read 0x0000.
Each output data register uses the bit assignments shown in Figure 13. The ND flag indicates that unread data resides in the output data registers. This flag clears and returns to 0 during an output register read sequence. It returns to 1 after the next internal sample updates the registers with new data. The EA flag indicates that one of the error flags in the DIAG_STAT register (see Table 21) is active (true). The remaining 14 bits are for data.
MSB FOR 14-BIT OUTPUT ND EA MSB FOR 12-BIT OUTPUT
07842-013
Gyroscope Precision Automatic Bias Null Calibration
Set GLOB_CMD[4] = 1 (DIN = 0xBE10) to execute this function, which takes the sensor offline for 30 sec while it collects a set of XGYRO_OUT data and calculates a more accurate bias correction factor. Once calculated, the correction factor loads into XGYRO_OFF, all sensor data resets to 0, and the flash memory updates automatically (50 ms). See Table 12.
Restoring Factory Calibration
Set GLOB_CMD[1] = 1 (DIN = 0xBE02) to execute this function, which resets each user calibration register (see Table 10 and Table 11) to 0x0000, resets all sensor data to 0, and automatically updates the flash memory (50 ms). See Table 12.
Figure 13. Output Register Bit Assignments
Auxiliary ADC
The AUX_ADC register provides access to the auxiliary ADC input channel. The ADC is a 12-bit successive approximation converter, which has an equivalent input circuit to the one in Figure 14. The maximum input range is +3.3 V. The ESD protection diodes can handle 10 mA without causing irreversible damage. The switch on-resistance (R1) has a typical value of 100 . The sampling capacitor, C2, has a typical value of 16 pF.
Linear Acceleration Bias Compensation (Gyroscope)
Set MSC_CTRL[7] = 1 (DIN = 0xB486) to enable correction for low frequency acceleration influences on gyroscope bias. Note that the DIN sequence also preserves the factory default condition for the data ready function (see Table 17).
Rev. PrA | Page 11 of 16
ADIS16364
OPERATIONAL CONTROL
Global Commands
The GLOB_CMD register provides trigger bits for several useful functions. Setting the assigned bit to 1 starts each operation, which returns to the bit to 0 after completion. For example, set GLOB_CMD[7] = 1 (DIN = 0xBE80) to execute a software reset, which stops the sensor operation and runs the device through its start-up sequence. This includes loading the control registers with their respective flash memory locations prior to producing new data. Reading the GLOB_CMD registers (DIN = 0x3E00) starts the burst mode read sequence. Table 12. GLOB_CMD
Bits [15:8] [7] [6:5] [4] [3] [2] [1] [0] Description Not used Software reset command Not used Precision autonull command Flash update command Auxiliary DAC data latch Factory calibration restore command Autonull command Bit [15:9] [8] [7:0]
Preliminary Technical Data
Table 14. SLP_CNT
Description Not used Indefinite sleep mode, set to 1 Programmable time bits, 0.5 sec/LSB
Digital Filtering
A programmable low-pass filtering provides additional opportunity for noise reduction on the inertial sensor outputs. This filter contains two cascaded averaging filters that provide a Bartlett window, FIR filter response (see Figure 15). SENS_AVG[2:0] controls the number of taps in each averaging stage. For example, SENS_AVG[2:0] = 110 sets each stage tap to 64.
0
-20 -40
MAGNITUDE (dB)
-60
-80 -100 N=2 N=4 N = 16 N = 64 0.01 0.1 1
07570-010
Internal Sample Rate
The ADIS16364 performs best when the sample rate is set to the factory default setting of 819.2 SPS. For applications that value lower sample rates, the SMPL_PRD register controls the ADIS16364 internal sample (see Table 13), and the following relationship produces the sample rate: tS = tB x NS + 1 Table 13. SMPL_PRD
Bit [15:8] [7] [6:0] Description Not used Time base (tB) 0 = 0.61035 ms, 1 = 18.921 ms Increment setting (NS) Internal sample period = tS = tB x NS + 1
-120 -140 0.001
FREQUENCY (f/fS)
Figure 15. Bartlett Window FIR Frequency Response (Phase = M Samples)
Dynamic Range
There are three dynamic range settings for the gyroscope: 75/sec, 150/sec, and 300/sec. The lower dynamic range settings (75/sec and 150/sec) limit the minimum filter tap sizes to maintain the resolution as the measurement range decreases. The recommended order for programming the SENS_AVG register is upper byte (sensitivity), followed by lower byte (filtering). For example, set SENS_AVG[10:8] = 010 (DIN = 0xB902) for a measurement range to 150/sec. Table 15. SENS_AVG
Bits [15:11] [10:8] Value Description Not used Measurement range (sensitivity) selection 300/sec (default condition) 150/sec, filter taps 4 (Bits[2:0] 0x02) 75/sec, filter taps 16 (Bits[2:0] 0x04) Not used Number of taps in each stage N = 2M
For example, set SMPL_PRD[7:0] = 0x0A (DIN = 0xB60A) for an internal sample period of 6.7 ms (sample rate = 149 SPS). For systems that value lower sample rates, in-system characterization can help determine performance trade-offs.
Power Management
Setting SMPL_PRD 0x0A also sets the sensor in low power mode. In addition to sensor performance, this mode also affects SPI data rates (see Table 2). Two sleep mode options are listed in Table 14. Set SLP_CNT[8] = 1 (DIN = 0xBB01) to start the indefinite sleep mode, which requires CS assertion (high to low), reset, or power cycle to wake-up. Set SLP_CNT[7:0] = 0x64 (DIN = 0xBA64) to put the ADIS16364 to sleep for 100 sec, as an example of the programmable sleep time option.
100 010 001 [7:3] [2:0]
Rev. PrA | Page 12 of 16
Preliminary Technical Data
INPUT/OUTPUT FUNCTIONS
General-Purpose I/O
DIO1, DIO2, DIO3, and DIO4 are configurable, general-purpose I/O lines that serve multiple purposes according to the following control register priority: MSC_CTRL, ALM_CTRL, and GPIO_CTRL. For example, set GPIO_CTRL = 0x080C (DIN = 0xB508, then 0xB40C) to set DIO1 and DIO2 as inputs and DIO3 and DIO4 as outputs, with DIO3 set low and DIO4 set high. Table 16. GPIO_CTRL
Bit [15:12] [11] [10] [9] [8] [7:4] [3] [2] [1] [0] Description Not used General-Purpose I/O Line 4 (DIO4) data level General-Purpose I/O Line 3 (DIO3) data level General-Purpose I/O Line 2 (DIO2) data level General-Purpose I/O Line 1 (DIO1) data level Not used General-Purpose I/O Line 4 (DIO4), direction control 1 = output, 0 = input General-Purpose I/O Line 3 (DIO3), direction control 1 = output, 0 = input General-Purpose I/O Line 2 (DIO2), direction control 1 = output, 0 = input General-Purpose I/O Line 1 (DIO1), direction control 1 = output, 0 = input
ADIS16364
Table 17. MSC_CTRL
Bits [15:12] [11] [10] [9] [8] [7] [6] [5:3] [2] [1] [0] Description Not used Memory test (clears on completion) 1 = enabled, 0 = disabled Internal self-test enable (clears on completion) 1 = enabled, 0 = disabled Manual self-test, negative stimulus 1 = enabled, 0 = disabled Manual self-test, positive stimulus 1 = enabled, 0 = disabled Linear acceleration bias compensation for gyroscopes 1 = enabled, 0 = disabled Linear accelerometer origin alignment 1 = enabled, 0 = disabled Not used Data ready enable 1 = enabled, 0 = disabled Data ready polarity 1 = active high, 0 = active low Data ready line select 1 = DIO2, 0 = DIO1
Auxiliary DAC
The 12-bit AUX_DAC line can drive its output to within 5 mV of the ground reference when it is not sinking current. As the output approaches 0 V, the linearity begins to degrade (~100 LSB beginning point). As the sink current increases, the nonlinear range increases. The DAC latch command moves the values of the AUX_DAC register into the DAC input register, enabling both bytes to take effect at the same time. Table 18. AUX_DAC
Bit [15:12] [11:0] Description Not used Data bits, scale factor = 0.8059 mV/code Offset binary format, 0 V = 0 codes
Input Clock Configuration
The input clock configuration function allows for external control over sampling in the ADIS16364. Set GPIO_CTRL[3] = 0 (DIN = 0x0B200) and SMPL_PRD[7:0] = 0x00 (DIN = 0xB600) to enable this function. See Table 2 and Figure 4 for timing information.
Data Ready I/O Indicator
The factory default sets DIO1 as a positive data ready indicator signal. The MSC_CTRL[2:0] register provides configuration options for changing this. For example, set MSC_CTRL[2:0] = 100 (DIN = 0xB404) to change the polarity of the data ready signal for interrupt inputs that require negative logic inputs for activation. The pulse width will be between 100 s and 200 s over all conditions.
Table 19. Setting AUX_DAC = 1 V
DIN 0xB0D9 0xB104 0xBE04 Descripition AUX_DAC[7:0] = 0xD9 (217 LSB). AUX_DAC[15:8] = 0x04 (1024 LSB). GLOB_CMD[2] = 1. Move values into the DAC input register, resulting in a 1 V output level.
Rev. PrA | Page 13 of 16
ADIS16364
DIAGNOSTICS
Self-Test
Self-test offers the opportunity to verify the mechanical integrity of each MEMS sensor. It applies an electrostatic force to each sensor element, which results in mechanical displacement that simulates a response to actual motion. Table 1 lists the expected response for each sensor, which provides pass/fail criteria. Set MSC_CTRL[10] = 1 (DIN = 0xB504) to run the internal self-test routine, which exercises all inertial sensors, measures each response, makes pass/fail decisions, and reports them to error flags in the DIAG_STAT register. MSC_CTRL[10] resets itself to 0 after completing the routine. MSC_CTRL[9:8] (DIN = 0xB502 or 0xB501) provides manual control over the self-test function. Table 20 gives an example test flow for using this option. Table 20. Manual Self-Test Example Sequence
DIN 0xB601 0xB904 0xB802 0x0400 0x0600 0x0800 0x0A00 0xB502 0x0400 Description SMPL_PRD[7:0] = 0x01, sample rate = 819.2 SPS. SENS_AVG[15:8] = 0x04, gyro range = 300/sec. SENS_AVG[7:0] = 0x02, 4-tap averaging filter. Delay = 50 ms. Read XGYRO_OUT. Read XACCL_OUT. Read YACCL_OUT. Read ZACCL_OUT. MSC_CTRL[9] = 1, gyroscope negative self-test. Delay = 50 ms. Read XGYRO_OUT. Determine whether the bias in the gyroscope output changes according to the expectation set in Table 2. MSC_CTRL[9:8] = 01, gyroscope/accelerometer positive self-test. Delay = 50 ms. Read XGYRO_OUT. Read XACCL_OUT. Read YACCL_OUT. Read ZACCL_OUT Determine whether the bias in the gyroscope and accelerometers changed according to the expectation set in Table 2. MSC_CTRL[15:8] = 0x00.
Preliminary Technical Data
Status
The error flags provide indicator functions for common system level issues. All of the flags clear (set to 0) after each DIAG_STAT register read cycle. If an error condition remains, the error flag returns to 1 during the next sample cycle. DIAG_STAT[1:0] does not require a read of this register to return to 0. If the power supply voltage goes back into range, these two flags clear automatically. Table 21. DIAG_STAT Bit Descriptions
Bit [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Description Z-axis accelerometer self-test failure (1 = fail, 0 = pass) Y-axis accelerometer self-test failure (1 = fail, 0 = pass) X-axis accelerometer self-test failure (1 = fail, 0 = pass) X-axis gyroscope self-test failure (1 = fail, 0 = pass) Y-axis gyroscope self-test failure (1 = fail, 0 = pass) Z-axis gyroscope self-test failure (1 = fail, 0 = pass) Alarm 2 status (1 = active, 0 = inactive) Alarm 1 status (1 = active, 0 = inactive) Not used Flash test, checksum flag (1 = fail, 0 = pass) Self-test diagnostic error flag (1 = fail, 0 = pass) Sensor overrange (1 = fail, 0 = pass) SPI communications failure (1 = fail, 0 = pass) Flash update failed (1 = fail, 0 = pass) Power supply above 5.25 V 1 = power supply 5.25 V, 0 = power supply 5.25 V Power supply below 4.75 V 1 = power supply 4.75 V, 0 = power supply 4.75 V
Alarm Registers
The alarm function provides monitoring for two independent conditions. The ALM_CTRL register provides control inputs for data source, data filtering (prior to comparison), static comparison, dynamic rate-of-change comparison, and output indicator configurations. The ALM_MAGx registers establish the trigger threshold and polarity configurations. Table 25 gives an example of how to configure a static alarm. The ALM_SMPLx registers provide the numbers of samples to use in the dynamic rate-of-change configuration. The period equals the number in the ALM_SMPLx register, multiplied by the sample period time, established by the SMPL_PRD register. See Table 26 for an example of how to configure the sensor for this type of function.
0xB501
0x0400 0x0600 0x0800 0x0A00
0xB500
Zero motion provides results that are more reliable. The settings in Table 20 are flexible and provide opportunity for optimization around speed and noise influence. For example, lowering the filtering taps decreases delay times but increases the opportunity for noise influence.
Memory Test
Setting MSC_CTRL[11] = 1 (DIN = 0xB508) performs a checksum verification of the flash memory locations. The pass/fail criteria load into the DIAG_STAT[6] register.
Rev. PrA | Page 14 of 16
Preliminary Technical Data
Table 22. ALM_MAG1, ALM_MAG2
Bit [15] [14] [13:0] Description Comparison polarity 1 = greater than, 0 = less than Not used Data bits that match the format of the trigger source selection
ADIS16364
Table 25. Alarm Configuration Example 1
DIN 0xAF55, 0xAE17 Description ALM_CTRL = 0x5517. Alarm 1 input = XACCL_OUT. Alarm 2 input = XACCL_OUT. Static level comparison, filtered data. DIO2 output indicator, positive polarity. ALM_MAG1 = 0x8341. Alarm 1 is true if XACCL_OUT > 0.5 g. ALM_MAG2= 0x3CBF. Alarm 2 is true if XACCL_OUT < -0.5 g.
Table 23. ALM_SMPL1, ALM_SMPL2
Bit [15:8] [7:0] Description Not used Data bits: number of samples (both 0x00 and 0x01 = 1)
0xA783, 0xA641 0xA93C, 0xA8BF
Table 24. ALM_CTRL Bit Designations
Bits [15:12] Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 [11:8] [7] [6] [5] [4] [3] [2] [1] [0]
1
Table 26. Alarm Configuration Example 2
DIN 0xAF76, 0xAE87 Description ALM_CTRL = 0x7687. Alarm 1 input = ZACCL_OUT. Alarm 2 input = YACCL_OUT. Rate of change comparison, unfiltered data. DIO2 output indicator, positive polarity. SMPL_PRD = 0x0001. Sample rate = 819.2 SPS. ALM_SMPL1 = 0x0008. Alarm 1 rate of change period = 9.77 ms. ALM_SMPL2= 0x0050. Alarm 2 rate of change period = 97.7 ms. ALM_MAG1 = 0x8341. Alarm 1 is true if XACCL_OUT > 0.5 g. ALM_MAG2= 0x3CBE. Alarm 2 is true if XACCL_OUT < -0.5 g.
Description Alarm 2 source selection Disable Power supply output X-axis gyroscope output Y-axis gyroscope output Z-axis gyroscope output X-axis accelerometer output Y-axis accelerometer output Z-axis accelerometer output Gyroscope temperature output X-axis inclinometer output Y-axis inclinometer output Auxiliary ADC input Alarm 1 source selection (same as Alarm 2) Rate of change (ROC) enable for Alarm 2 1 = rate of change, 0 = static level Rate of change (ROC) enable for Alarm 1 1 = rate of change, 0 = static level Not used Comparison data filter setting1 1 = filtered data, 0 = unfiltered data Not used Alarm output enable 1 = enabled, 0 = disabled Alarm output polarity 1 = active high, 0 = active low Alarm output line select 1 = DIO2, 0 = DIO1
0xB601 0xAB08 0xAC50 0xA783, 0xA641 0xA93C, 0xA8BE
Incline outputs always use filtered data in this comparison.
Rev. PrA | Page 15 of 16
ADIS16364 OUTLINE DIMENSIONS
Preliminary Technical Data
31.900 31.700 31.500 23.454 23.200 22.946 2.382 BSC 9.464 9.210 8.956 (2x) 4.20 4.00 3.80 (2x)
1.588 BSC TOP VIEW 1.588 BSC 22.964 22.710 22.456
17.41 17.21 17.01 (2x)
BOTTOM VIEW
21.410 21.210 21.010
10.60 BSC
PIN 24
14.950 14.550 14.150 10.50 BSC FRONT VIEW
5.20 5.00 4.80 (2x)
1.00 BSC
7.18 BSC
PIN 1
0.05 BSC
2.00 BSC 12.10 BSC
23.504 23.250 22.996 2.660 2.500 2.340 SIDE VIEW DETAIL A DETAIL A 4.162 BSC 4.330 BSC
0.305 BSC (24x)
1.00 BSC (22x) 14.00 BSC
1.65 BSC
011108-C
Figure 16. 24-Lead Module with Connector Interface (ML-24-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADIS16364BMLZ1 ADIS16364/PCBZ1
1
Temperature Range -40C to +105C
Package Description 24-Lead Module with Connector Interface Interface Board
Package Option ML-24-2
Z = RoHS Compliant Part.
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07906-0-11/08(PrA)
Rev. PrA | Page 16 of 16

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